Published February 1989
| Version v1
Journal article
A fastbus flash ADC system for the Mark II Vertex chamber
Description
This is a description of a flash ADC system built for the Mark II experimental at the Stanford Linear Accelerator Center (SLAC). This system was designed for use in the experiment's vertex chamber where signals could occur over a relatively long time, approximately 10 microseconds. This long time, coupled with fast cable amplifiers, necessitated an alternate design approach than was used with a dE/dX FASTBUS flash ADC design
Additional details
Publishing Information
- Journal Title
- IEEE Transactions on Nuclear Science
- Journal Volume
- 36
- Journal Issue
- 1
- Series
- IEEE Trans. Nucl. Sci.
- Journal Page Range
- 643-645
- ISSN
- 0018-9499
- CODEN
- IETNA
Conference
- Title
- IEEE nuclear science symposium.
- Dates
- 9-11 Nov 1988.
- Place
- Orlando, FL (USA).
INIS
- Country of Publication
- United States
- Country of Input or Organization
- United States
- INIS RN
- 20057016
- Subject category
- S43: PARTICLE ACCELERATORS; S99: GENERAL AND MISCELLANEOUS;
- Resource subtype / Literary indicator
- Conference
- Descriptors DEI
- AMPLIFIERS; ANALOG-TO-DIGITAL CONVERTERS; FASTBUS SYSTEM; SPECIFICATIONS; STANFORD LINEAR ACCELERATOR CE
- Descriptors DEC
- ELECTRONIC EQUIPMENT; EQUIPMENT; NATIONAL ORGANIZATIONS; US DOE; US ERDA; US ORGANIZATIONS
Optional Information
- Secondary number(s)
- CONF-881103--.