Voltammetric investigation of porous silicon for integrated circuit applications

Integrated circuits fabricated using the method of full dielectric isolation have several advantages when compared to circuits isolated by p-n junctions. Since device isolation is simple, and parasitic capacitance are reduced, high packing densities and high device speeds can be realized. In addition, full dielectric isolation reduces latch-up and the sensitivity of devices to ionizing radiation effects. Silicon-on-insulator (SOI) is the generic name for one class of devices with complete dielectric isolation. There are several techniques for achieving desired SOI structures, including zone melt recrystallization, high dose oxygen or nitrogen implantation, and oxidation of porous silicon. The authors utilize the directed growth of porous silicon (PS) to isolate silicon islands upon which microcircuits are fabricated. The porous silicon is then thermally oxidized to produce a fully dense, insulating silicon dioxide layer