Evaluation of a feature extraction framework for FPGA firmware generation during a beam-test at CERN-SPS for the CBM-TRD experiment

A feature extraction framework has been developed to allow easy FPGA firmware generation for specific feature extraction algorithms in order to find and extract regions of interest within time-based signals. This framework allows the instantiation of multiple well-known feature extraction algorithms such as center of gravity, time over threshold and cluster finder, just to mention a few of them. A graphical user interface has also been built on top of the framework to provide a user-friendly way to visualize the data-flow architecture across processing stages. The FPGA platform constraints are automatically set up by the framework itself. This feature reduces the need of low-level hardware configuration knowledge that would normally be provided by the user, centering the attention in setting up the processing algorithms for the given task more than in writing hardware description code. During November 2015, a beam-test was performed at the CERN-SPS hall. The presented framework was used to generate a firmware for the SysCore3 FPGA development board used to readout two TRD detectors by means of the SPADIC 1.0 front-end chip. The framework architecture, design methodology, as well as the achieved results during the mentioned beam-test are presented.