A 30MHz FASTBUS transient digitizer data compactor using CMOS gate arrays

A 16 channel data compactor built at TRIUMF for the BNL787 experiment is described. The module is designed to compact data from a 16-channel 256 bin 500MHz CCD Transient Digitizer. Each channel accepts 8-bit digitized data from a CCD module, performs pedestal subtraction, spike and zero-suppression, and formats the data together with channel identifiers into 32-bit words for readout by FASTBUS. Data compaction is performed on-the-fly at a 30MHz rate, with a 600ns initial delay. Data for all channels may be read out in one FASTBUS block transfer operation. The module incorporates a fully-featured FASTBUS slave interface built using a CMOS gate array (the PCL) and two bipolar gate arrays (ADIs)