Characterization of through silicon vias (TSVs) on the ATLAS pixel chip

The high luminosity upgrade of the LHC requires new ATLAS detector systems. In particular the inner tracking system will be upgraded to an all-silicon detector covering an area of about 200m², demanding new module technologies. New interconnection techniques allow area efficient optimisation module designs. A key element therein is the so-called through silicon via (TSV) applied through the FE-chip. It allows for minimized passive area, less or no wirebonds, and 4-side abuttable modules. We report on TSV fabrication and characterisation in a Bonn/IZM-Berlin collaboration. Processing of a sample of FE-I4B bare chips, a readout chip for 26880 hybrid pixels designed in a 130nm CMOS process for use in the ATLAS IBL, has been completed. In this talk the IZM via last process on ATLAS FE-I4B chips is presented with focus on via resistance and process yield.