Published November 10, 1983 | Version v1
Journal article Metadata-only

CMOS logic circuit optimum design for radiation tolerance

Creators

  • 1. Toshiba Corp., Kawasaki, Kanagawa (Japan)

Description

CMOS logic circuit optimum design for radiation tolerance has been investigated, based on NMOS and PMOS transistor parameter shift data due to radiation effects. The DC noise immunity for the three-input NAND has been found to be 36% greater than for the three-input NOR. The gate area for the optimised NAND is about three times smaller than that for the optimised NOR. (author)

Additional details

Publishing Information

Journal Title
Electron. Lett.
Journal Volume
19
Journal Issue
23
Series
Electron. Lett.
Journal Page Range
977-979
ISSN
0013-5194

INIS

Country of Publication
United Kingdom
Country of Input or Organization
United Kingdom
INIS RN
15025752
Subject category
S46: INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY;
Descriptors DEI
DIRECT CURRENT; IONIZING RADIATIONS; LOGIC CIRCUITS; MOS TRANSISTORS; N-TYPE CONDUCTORS; NOISE; P-TYPE CONDUCTORS; RADIATION HARDENING; REACTOR COMPONENTS
Descriptors DEC
CURRENTS; ELECTRIC CURRENTS; ELECTRONIC CIRCUITS; HARDENING; MATERIALS; PHYSICAL RADIATION EFFECTS; RADIATION EFFECTS; RADIATIONS; SEMICONDUCTOR DEVICES; SEMICONDUCTOR MATERIALS; TRANSISTORS