A 0.7–7 GHz wideband reconfigurable receiver RF front-end in CMOS

A 0.7–7 GHz wideband RF receiver front-end SoC is designed using the CMOS process. The front-end is composed of two main blocks: a single-ended wideband low noise amplifier (LNA) and an in-phase/quadrature (I/Q) voltage-driven passive mixer with IF amplifiers. Based on a self-biased resistive negative feedback topology, the LNA adopts shunt-peaking inductors and a gate inductor to boost the bandwidth. The passive down-conversion mixer includes two parts: passive switches and IF amplifiers. The measurement results show that the front-end works well at different LO frequencies, and this chip is reconfigurable among 0.7 to 7 GHz by tuning the LO frequency. The measured results under 2.5-GHz LO frequency show that the front-end SoC achieves a maximum conversion gain of 26 dB, a minimum noise figure (NF) of 3.2 dB, with an IF bandwidth of greater than 500 MHz. The chip area is 1.67 × 1.08 mm². (paper)