InP/low-temperature-deposited SiO2 interface

This paper describes the characteristics of the InP/low-temperature-deposited SiO2 MIS system, with emphasis on C-V hysteresis and drain current drift in InP MISFETs. The SiO2 was deposited using a low- pressure (2 Torr) Hg-assisted UV deposition system using SiH4 and N2O as source gases. Depositions were carried out at substrate temperatures of 75 degrees C to 170 degrees C. MIS capacitors, fabricated on n-epi/n+-InP substrates (to minimize series resistance) with Al or Ti/Pt/Au metallizations were characterized using C-V measurements. The authors show that long-term (16 h 300 degrees C in H2) anneals reduces interface state density (Dit), oxide fixed charge, and C-V hysteresis, Dit values of <1x1011 cm-2eV-1, adequate for good MISFET operation, were routinely obtained over a large portion of the bandgap. InP MISFETs with 1-μm gatelength fabricated with this oxide showed good performance at 20 GHz