Design of a fast and low-power consumption shaper

An integrated CMOS high-speed, low power consumption shaper has been designed for the portable digital radiography detector. Analytical simulations of CR-(RC)ⁿ semi-Gaussian shaper of various order and shaping time constant were carried out to optimize the timing performance, keeping in mind the stringent requirements of power consumption and equivalent noise charge (ENC). The input differential transistors working in weak inversion are presented to achieve low-power consumption. There is no undershoot by using nested feedback loop. The chip is designed in 0.5 DPDM process by CSMC. Considering a fast signal peaking time of 250 ns, the power consumption is 34.5 μW and the ENC is 453e for a detector of 20 pf. (authors)