Design of global high precision clock synchronization based on jitter cleaner circuit

In the nuclear electronics clock distribution system based on serializer/deserializer (SerDes), jitter will gradually accumulate. In order to solve this problem, a clock jitter cleaner circuit based on phase-locked loop (PLL) is designed. By selecting the appropriate loop filter bandwidth, clock jitter can be reduced to about 9 ps. In order to estimate the maximum series of clock distribution, a model of additional clock jitter is built. Test results show that the clock jitter cleaner circuit can guarantee the global clock successfully distributed, and can be referenced and used in practical engineering design. (authors)