A 10 Gb/s burst-mode clock and data recovery circuit

We introduce a gated oscillator based on XONR/XOR cells and illustrate its working process. A half-rate BM-CDR circuit based on the proposed oscillator is designed, and the design is implemented in SMIC 0.13 μm CMOS technology occupying an area of 675 × 25 μm2. The measured results show that this circuit can recover clock and data from each 10 Gbit/s burst-mode data packet within 5 bits, and the recovered data pass eye-mask test defined in IEEE standard 802.3av. (semiconductor integrated circuits)