Published 1999 | Version v1
Miscellaneous Open

Latent interface-trap building in power VDMOSFETs: new experimental evidence and numerical simulation

Creators

  • 1. Faculty of Electronic Engineering, Nis (Yugoslavia)

Description

The paper presents new experimental evidence of the latent interface-trap buildup during annealing of gamma-ray irradiated power VDMOSFETs. We try to reveal the nature of this still ill-understood phenomenon by isothermal annealing, switching temperature annealing and switching bias annealing experiments. The results of numerical simulation of interface-trap kinetics during annealing are also shown. (authors)

Availability note (English)

Available from INIS in electronic form

Files

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Additional details

Additional titles

Original title (English)
Formation latente d'etats d'interface dans les transistors de puissance VDMOSFETs: nouvelle evidence experimentale et simulation numerique

Publishing Information

Imprint Pagination
[4 p.]
Report number
INIS-FR--2037

Conference

Title
5. European conference on radiation and its effects on components and systems
Original Conference Title
5. congres europeen les radiations et leurs effets sur les composants et les systemes
Dates
13-17 Sep 1999
Place
Abbaye de Fontevraud (France)

INIS

Country of Publication
France
Country of Input or Organization
France
INIS RN
34078031
Subject category
S46: INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY;
Resource subtype / Literary indicator
Conference
Descriptors DEI
ANNEALING; CHARGE TRANSPORT; GAMMA RADIATION; MOSFET; PHYSICAL RADIATION EFFECTS; TRAPS
Descriptors DEC
ELECTROMAGNETIC RADIATION; FIELD EFFECT TRANSISTORS; HEAT TREATMENTS; IONIZING RADIATIONS; MOS TRANSISTORS; RADIATION EFFECTS; RADIATIONS; SEMICONDUCTOR DEVICES; TRANSISTORS

Optional Information

Notes
8 refs.