The cathode strip chamber data acquisition electronics for CMS
- 1. Department of Physics, Ohio State University, 191 West Woodruff Avenue, Columbus, OH 43210 (United States)
Description
Data Acquisition (DAQ) electronics for Cathode Strip Chambers (CSC) [CMS Collaboration, The Muon Project Technical Design Report, CERN/LHCC 97-32, CMS TDR3, 1997] in the Compact Muon Solenoid (CMS) [CMS Collaboration, The Compact Muon Solenoid Technical Proposal, CERN/LHCC 94-38, 1994] experiment at the Large Hadron Collider (LHC) [The LHC study group, The Large Hadron Collider: Conceptual Design, CERN/AC 1995-05, 1995] is described. The CSC DAQ system [B. Bylsma, et al., in: Proceedings of the Topical Workshop on Electronics for Particle Physics, Prague, Czech Republic, CERN-2007-007, 2007, pp. 195-198] includes on-detector and off-detector electronics, encompassing five different types of custom circuit boards designed to handle the high event rate at the LHC. The on-detector electronics includes Cathode Front End Boards (CFEB) [R. Breedon, et al., Nucl. Instr. and Meth. A 471 (2001) 340], which amplify, shape, store, and digitize chamber cathode signals; Anode Front End Boards (AFEB) [T. Ferguson, et al., Nucl. Instr. and Meth. A 539 (2005) 386], which amplify, shape and discriminate chamber anode signals; and Data Acquisition Motherboards (DAQMB), which controls the on-chamber electronics and the readout of the chamber. The off-detector electronics, located in the underground service cavern, includes Detector Dependent Unit (DDU) boards, which perform real time data error checking, electronics reset requests and data concentration; and Data Concentrator Card (DCC) boards, which further compact the data and send it to the CMS DAQ System [CMS Collaboration, The TriDAS Project Technical Design Report, Volume 2: Data Acquisition and High-level Trigger, CERN/LHCC 2002-26, 2002], and serve as an interface to the CMS Trigger Timing Control (TTC) [TTC system ] system. Application Specific Integrated Circuits (ASIC) are utilized for analogous signal processing on front end boards. Field Programmable Gate Arrays (FPGA) are utilized on all boards in the system to provide programmability. The DAQ system has been installed and commissioned, and is ready for LHC data taking.
Availability note (English)
Available from http://dx.doi.org/10.1016/j.nima.2008.12.141Additional details
Identifiers
- DOI
- 10.1016/j.nima.2008.12.141;
- PII
- S0168-9002(08)02115-3;
Publishing Information
- Journal Title
- Nuclear Instruments and Methods in Physics Research. Section A, Accelerators, Spectrometers, Detectors and Associated Equipment
- Journal Volume
- 600
- Journal Issue
- 3
- Journal Page Range
- p. 661-672
- ISSN
- 0168-9002
- CODEN
- NIMAER
INIS
- Country of Publication
- Netherlands
- Country of Input or Organization
- International Atomic Energy Agency (IAEA)
- INIS RN
- 41029089
- Subject category
- S46: INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY;
- Descriptors DEI
- ANODES; CATHODES; CERN LHC; CONTROL; DATA ACQUISITION; DESIGN; ERRORS; INTEGRATED CIRCUITS; MUONS; READOUT SYSTEMS; SAFETY REPORTS; SIGNALS; SOLENOIDS; UNDERGROUND
- Descriptors DEC
- ACCELERATORS; CYCLIC ACCELERATORS; ELECTRIC COILS; ELECTRICAL EQUIPMENT; ELECTRODES; ELECTRONIC CIRCUITS; ELEMENTARY PARTICLES; EQUIPMENT; FERMIONS; LEPTONS; LEVELS; MICROELECTRONIC CIRCUITS; STORAGE RINGS; SYNCHROTRONS
Optional Information
- Copyright
- Copyright (c) 2008 Elsevier Science B.V., Amsterdam, The Netherlands, All rights reserved.