A 0.5 V divider-by-2 design with optimization methods for wireless sensor networks

A 0.5 V static master-slave D flip-flop (DFF) divider-by-2 is implemented with a 0.13 μm 1P8M RF-mixed signal CMOS process. Low-threshold transistors in a deep-N well with forward-body bias technology are used in the circuit. Each of the D-latch with source coupled logic consists of sensing and latching circuits. To increase the maximum operating frequency and decrease power consumption, the latching current is one half of the sensing current. The circuit optimization methods are described in this paper. The measured maximum operating frequency is 6.5 GHz and the minimum input singled-signal amplitude is 0.15 V. (semiconductor integrated circuits)