Micro-trench free 4H-SiC etching with improved SiC/SiO₂ selectivity using inductively coupled SF₆/O₂/Ar plasma

SiC dry etching process for formation of a trenched-gate structure in trench metal-oxide-semiconductor field-effect-transistors employing bottom protection p-well (BPW) has been investigated. SF₆/O₂/Ar based inductively-coupled-plasma reactive-ion-etching were utilized with various variations in process parameters, such as bias power, ICP power, kind of gas species, working pressure and temperature. The effects of process parameters on trench profiles were analyzed by a cross-sectional scanning electron microscope and profilometer to suppress micro trenches at a bottom corner of the trench and improve SiC/SiO₂ etch selectivity. We successfully demonstrated the micro-trench free SiC trench structure with high SiC/SiO₂ etch selectivity of 3.7 at bias power of 1 kW, ICP power of 4 kW, SF₆/O₂/Ar flows of 6/6/8 sccm, working pressure of 15 mTorr and temperature of 20 °C. (paper)