A general design method for full-frame area array CCD driving sequence generator based on sequence subdivision and finite state machine

To provide a general design method for a CCD timing drive, a simple CCD driving circuit design is presented. First, the internal structure and working mode of area array CCD485 are introduced, and its basic driving circuit design is given. Then, through the analysis of the driving sequence diagram of area array CCD485, the normal operation of a full-frame large-area array CCD is analyzed. A design method for a universal full-frame array CCD driving timing generator based on time sequence subdivision and a finite state machine is proposed. By grouping the driving timing of the CCD, each group of timing waveforms is divided into several basic output states. In this manner, the driving sequence needed in each working stage of the CCD can be obtained by combining the basic states, which are described by a Moore finite state machine, and the timing driver is modularized. A timing generator supporting the normal operation of a full-frame area array CCD is designed. The specific design of each module for generating the timing is given. The design process of the generator is simple. Finally, a CCD driving timing generator is designed by using Xilinx's Virtex-II Pro series FPGA-XC2VP20 and Xilinx's ISE software platform, and the waveform is simulated and analyzed. The output signal fully meets the driving timing requirements of the 485 chip, which proves the validity of the design method.