Published September 2014 | Version v1
Journal article

Hysteresis analysis of graphene transistor under repeated test and gate voltage stress

  • 1. Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029 (China)
  • 2. College of Science, China University of Petroleum, Beijing 102249 (China)

Description

The current transport characteristic is studied systematically based on a back-gate graphene field effect transistor, under repeated test and gate voltage stress. The interface trapped charges caused by the gate voltage sweep process screens the gate electric field, and results in the neutral point voltage shift between the forth and back sweep direction. In the repeated test process, the neutral point voltage keeps increasing with test times in both forth and back sweeps, which indicates the existence of interface trapped electrons residual and accumulation. In gate voltage stress experiment, the relative neutral point voltage significantly decreases with the reducing of stress voltage, especially in −40 V, which illustrates the driven-out phenomenon of trapped electrons under negative voltage stress. (semiconductor devices)

Availability note (English)

Available from http://dx.doi.org/10.1088/1674-4926/35/9/094003

Additional details

Publishing Information

Journal Title
Journal of Semiconductors
Journal Volume
35
Journal Issue
9
Journal Page Range
[5 p.]
ISSN
1674-4926

INIS

Country of Publication
United Kingdom
Country of Input or Organization
International Atomic Energy Agency (IAEA)
INIS RN
47047640
Subject category
S36: MATERIALS SCIENCE;
Descriptors DEI
BUILDUP; ELECTRIC CURRENTS; ELECTRIC FIELDS; ELECTRIC POTENTIAL; FIELD EFFECT TRANSISTORS; GRAPHENE; HYSTERESIS; INTERFACES; STRESSES; TRAPPED ELECTRONS; TRAPPING
Descriptors DEC
CARBON; CURRENTS; ELECTRONS; ELEMENTARY PARTICLES; ELEMENTS; FERMIONS; LEPTONS; NONMETALS; SEMICONDUCTOR DEVICES; TRANSISTORS