Published 1988
| Version v1
Book
The contiguity processor: A SIMD architecture for a 2nd level track trigger
Creators
- 1. Istituto Nazionale di Fisica Nucleare, Genoa (Italy)
- 2. European Organization for Nuclear Research, Geneva (Switzerland)
Description
The contiguity processor (CP), designed for the Delphi time projection chamber (TPC), is a Fastbus 2nd level trigger processor, that makes heavy use of application specific integrated circuits (ASIC). The architecture is based on a bidimensional lattice of 4608 processing elements (PEs). Each of these PEs is connected with its 4 neighbours, and they all execute the same stream of instructions (single instruction multiple data architecture - SIMD). The CP instruction set is tailored to the special requirements of the contiguity algorithm. (author). 3 refs, 3 figs
Additional details
Publishing Information
- Publisher
- World Scientific.
- Imprint Place
- Singapore (Singapore)
- ISBN
- 9971-50-742-0
- Imprint Title
- International conference on the impact of digital microelectronics and microprocessors on particle physics
- Imprint Pagination
- 346 p.
- Journal Page Range
- p. 199-204.
Conference
- Title
- International conference on the impact of digital microelectronics and microprocessors on particle physics.
- Dates
- 28-30 Mar 1988.
- Place
- Trieste (Italy).
INIS
- Country of Publication
- Singapore
- Country of Input or Organization
- International Atomic Energy Agency (IAEA)
- INIS RN
- 23072223
- Subject category
- S46: INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY;
- Resource subtype / Literary indicator
- Conference
- Descriptors DEI
- COMPUTER ARCHITECTURE; FASTBUS SYSTEM; HIGH ENERGY PHYSICS; MEMORY DEVICES; MICROPROCESSORS; RADIATION DETECTORS; TRIGGER CIRCUITS
- Descriptors DEC
- ELECTRONIC CIRCUITS; MEASURING INSTRUMENTS; MICROELECTRONIC CIRCUITS; PHYSICS; PULSE CIRCUITS