JICG CMOS transistors for reduction of total ionizing dose and single event effects in a 130 nm bulk SiGe BiCMOS technology

Highlights: • TID induced drain leakage current reduction by lateral junction isolation of the MOS channel. • Small body sheet and contact resistance. • Narrow gate widths with junction isolated MOS transistors. • Improved radiation tolerance with triple well 130 nm bulk CMOS technology. • Isolated NMOS substantially reduces the vulnerability of digital CMOS circuits against SEEs. We report on a novel radiation hardening by design (RHBD) approach for mitigation of total ionization dose (TID) induced drain leakage currents and single event transient (SET) in digital circuits fabricated in a 130 nm bulk SiGe BiCMOS technology. In order to avoid significant TID induced increase of drain leakage currents for NMOS transistors and channel pinch-off for PMOS transistors due to positive charges trapped at the lateral shallow trench insulator silicon interface we introduced junction isolation (JI) for the lateral MOS channel regions. The device construction measures applied also support to suppress the generation SETs. The tolerance of JI MOS transistors against TID induced drain leakage currents was verified up to a TID > 1.3 Mrad(Si). SET tests performed at four different inverter types varying in the arrangement the deep well in the layout. For CMOS inverters with isolated NMOS transistors a LET threshold > 130 MeV cm² mg⁻¹ was obtained.