Published December 2010 | Version v1
Journal article

Process optimization of a deep trench isolation structure for high voltage SOI devices

  • 1. National ASIC System Engineering Research Center, Southeast University, Nanjing 210096 (China)

Description

The process reasons for weak point formation of the deep trench on SOI wafers have been analyzed in detail. An optimized trench process is also proposed. It is found that there are two main reasons: one is over-etching laterally of the silicon on the surface of the buried oxide caused by a fringe effect; and the other is the slow growth rate of the isolation oxide in the concave silicon corner of the trench bottom. In order to improve the isolation performance of the deep trench, two feasible ways for optimizing the trench process are proposed. The improved process thickens the isolation oxide and rounds sharp silicon corners at their weak points, increasing the applied voltage by 15-20 V at the same leakage current. The proposed new trench isolation process has been verified in the foundry's 0.5-μm HV SOI technology. (semiconductor devices)

Availability note (English)

Available from http://dx.doi.org/10.1088/1674-4926/31/12/124009

Additional details

Publishing Information

Journal Title
Journal of Semiconductors
Journal Volume
31
Journal Issue
12
Journal Page Range
[4 p.]
ISSN
1674-4926

INIS

Country of Publication
United Kingdom
Country of Input or Organization
International Atomic Energy Agency (IAEA)
INIS RN
43013281
Subject category
S36: MATERIALS SCIENCE;
Descriptors DEI
ELECTRIC POTENTIAL; EQUIPMENT; LEAKAGE CURRENT; OPTIMIZATION; OXIDES; SEMICONDUCTOR DEVICES; SILICON
Descriptors DEC
CHALCOGENIDES; CURRENTS; ELECTRIC CURRENTS; ELEMENTS; OXYGEN COMPOUNDS; SEMIMETALS