Published March 1, 1993 | Version v1
Journal article

A 66 MHz, 32-channel analog memory circuit with data selection for fast silicon detectors

  • 1. Cavendish Lab., Univ. Cambridge (United Kingdom)
  • 2. CERN, Geneva (Switzerland)
  • 3. Inst. fuer Physik, Univ. Dortmund (Germany)
  • 4. DPNC, Geneva Univ. (Switzerland)
  • 5. School of Physics, Univ. Melbourne, Parkville (Ausralia)
  • 6. Dept. of Nuclear Physics, Oxford Univ. (United Kingdom)
  • 7. Rutherford Appleton Lab., Chilton (United Kingdom)
  • 8. Centre d'Etudes Nucleaires de Saclay, 91 - Gif-sur-Yvette (France)

Description

An analog memory array with 64 memory cells for each channel has been designed and manufactured in CMOS. A new skip logic controller allows to write at 66 MHz without dead time and to read out at a lower frequency simultaneously. The input circuit is charge-sensitive and integrates continuously. Pedestal nonuniformity is 1.4 mV rms from cell-to-cell and 3.5 mV rms between channels. The linearity range is -2.5 to +1.5 V, which corresponds to 11 bits. The chip has been used in a particle detection test. (orig.)

Additional details

Publishing Information

Journal Title
Nuclear Instruments and Methods in Physics Research. Section A
Journal Volume
326
Journal Issue
1/2
Journal Page Range
p. 100-111.
ISSN
0168-9002
CODEN
NIMAER

Conference

Title
New developments on radiation detectors.
Acronym
6. European symposium on semiconductor detectors
Dates
24-26 Feb 1992.
Place
Milan (Italy).

Optional Information

Collaborations
RD2 Collaboration.