Simulation of adder circuit using reversible gates in verilog HDL

Power dissipation is one of the most important factors in VLSI design. Traditional and conventional gates, while having been widely adopted and found in usage in almost every industry, have some drawbacks. Classical gates while effective are irreversible in nature. Due to this irreversible nature, information is lost and results in heat dissipation. Part of the energy dissipation is due to the non-identity of switches. Although advancements in material science and fabrication processes have drastically reduced the power loss, on an overall scale there still exists energy dissipation. In a system, the energy loss is directly proportional to the number of bits or information lost/erased during the computation process. Reversible computation utilises one-is-to one mapping of inputs with respect to outputs and hence prevents bit loss. Minimum number of gates is used for operations while also minimising the heat. The physical interpretation of reversibility refers to the sending of charges slowly from one node to another, instead of them being dissipated. Thus, optimal energy efficiency is achieved. This study explores the field of reversible logic and utilizes Peres Gate to develop a Full Adder circuit that shows significant reduction in power consumption in simulations performed in Xilinx Vivado. We achieved a power consumption figure that is far lower along with about 10% reduction in Junction temperature, as compared to conventional Full Adder and have shown the methodology to create and obtain reversible gate full adder circuit in Xilinx Vivado