A 900 MHz fractional-N synthesizer for UHF transceiver in 0.18 μm CMOS technology

A 900 MHz fractional-N synthesizer is designed for the UHF transceiver. The VCO with a 4 bits capacitor bank covers 823–1061 MHz that implements 16 (2⁴) sub-bands. A 7/8 dual-modulus prescaler is implemented with a phase-switching circuit and high-speed flip—flops, which are composed of source coupled logic. The proposed synthesizer phase-locked loop is demonstrated with a 50 kHz band width by a low 12.95 MHz reference clock, and offers a better phase noise and band width tradeoff. To reduce the out-band phase noise, a 4-levels 3-order single-loop sigma—delta modulator is applied. When its relative frequency resolution is settled to 10⁻⁶, the testing results show that the phase noises are −120.6 dBc/Hz at 1 MHz and −95.0 dBc/Hz at 100 kHz. The chip is 2.1 mm² in UMC 0.18 μm CMOS. The power is 36 mW at a 1.8 V supply. (semiconductor integrated circuits)