Low frequency noise and electrical transport properties of pseudomorphic Si/Si1-xGex heterostructures

Growth of high germanium content (x=0.44) pseudomorphic Si/Si1-xGex structures at low temperature, followed by a high temperature anneal, was optimised for low temperature mobility. The optimum was found for growth at 380 deg C with an ex-situ anneal at 800 deg C which gave a 10K mobility of 1030cm2V-1s-1 with a sheet density of 1.2x1012cm-2. A sample grown at 380 deg C with an in-situ anneal at 800 deg C gave an even higher 10K mobility of 1985cm2V-1s-1 with a sheet density of 1.0x1012cm-2. Chemical etching was used to fully deplete the dopant supply layer so that a room temperature Hall mobility of 255cm2V-1s-1 was measured. Variation of the Hall coefficient was used to determine the room temperature Hall scattering factor as 0.58 which gave a Drift mobility of 440cm2V-1s-1 (about twice that of a conventional Si pMOS device at the same vertical electric field). Pseudomorphic Si/Si1-xGex pMOSFETs (x=0.36) with Si cap thicknesses of 2, 5 and 8nm were also investigated. Inversion charge extracted from CV measurements was used to determine the room temperature effective mobility. A peak mobility of 220cm2V-1s-1 was determined for a 5nm cap sample which was about twice that of the Si control. Interface trap densities from CV were found to increase with reduction of Si cap thickness. The deterioration in interface quality correlated with a reduction in peak mobility. Although the thickest cap sample had the highest peak mobility, mobility degradation with increased vertical field was rapid due to the early onset of parallel conduction in the Si cap. Mobility calculations were fitted to low temperature Hall measurements which provided a theoretical model of the mobility degradation. Scattering by oxide impurities was shown to decrease carrier mobility with an increased effect for thinner caps. For the thinnest cap sample an increase in interface impurities and hetero-interface roughness was required to explain the observed results. Low frequency (1/f) electrical noise measurements were performed in the linear region of operation for the above devices. 1/f noise was found to be about a decade lower in SiGe devices than in a Si control, with the greatest noise reduction for strong inversion. A number fluctuation model with a variation in the oxide trap density provided the best explanation of the observed results. Oxide trap densities determined from noise measurements were found to fall at the band edge towards mid-gap in accordance with the common 'U-shaped' distribution of trap states. Lower noise in SiGe devices was attributed to the valence band offset which caused a displacement of the Fermi level towards mid-gap, where the density of trap states is lower, resulting in lower noise. (author)