Analysis and optimization of current sensing circuit for deep sub-micron SRAM

A quantitative yield analysis of a traditional current sensing circuit considering the random dopant fluctuation effect is presented. It investigates the impact of transistor size, falling time of control signal CS and threshold voltage of critical transistors on failure probability of current sensing circuit. On this basis, we present a final optimization to improve the reliability of current sense amplifier. Under 90 nm process, simulation shows that failure probability of current sensing circuit can be reduced by 80% after optimization compared with the normal situation and the delay time only increases marginally. (semiconductor integrated circuits)