The optimal design of 15 nm gate-length junctionless SOI FinFETs for reducing leakage current

Junctionless (JL) transistors need to be heavily doped to have large drain current in the ON-state, which engenders the effect of band-to-band tunneling (BTBT) in the OFF-state simultaneously. It causes an obvious increase of the leakage current in the OFF-state. This paper presents an effective method of reducing the leakage current by changing the geometrical shape and dimension of the oxide layer under the edge of the gate. The optimal design of 15 nm gate-length JL silicon-on-insulator FinFETs with the triple-gate structure is performed for reducing the effect of BTBT through simulation and analysis by this means. (paper)