Radiation-hardened CMOS gate arrays

On the basis of fundamental research in radiation-tolerant devices, carried out as a part of the MITI Future Electron Device Project, a 4 k-gate radiation-hardened CMOS gate array has been developed for nuclear plant applications. The project has been managed by the Advanced Nuclear Equipment Research Institute (ANERI) sponsored by the Agency of Natural Resources and Energy, MITI. A 10 k-gate radiation-hardened CMOS gate array has also been developed for space applications. One hundred k-rads (Si) total dose radiation-hardness has been realized by introducing thin-field oxide between source/drain diffusion layers and thick field oxide in NMOS transistors. This is employed in both basic cells and I/O cells, along with a buried P+ diffusion layer at the P-well edge in basic cells, without sacrificing speed performance. (author)