Model to predict the number of transistors in an asymmetrical priority Address-Encoder and Reset-Decoder readout circuit for monolithic active pixel sensors for high-energy physics

The digital circuit layout in the active pixel sensor usually occupies the remaining area of an analog circuit layout. Thus, the number of transistors in the readout circuit is an important factor that enables the size of the implementation area to be predicted, when the digital layout of the readout circuit is placed in the specific area. Therefore, the requirement of reducing implementation area of the monolithic active pixel sensor in high-energy physics experiment make it is important to find the optimal readout circuit structure with minimum number of transistors. This study utilizes arithmetic and geometric series to propose a model to predict the number of transistors based on the Karnaugh map of the priority Address-Encoder and Reset-Decoder readout circuit. The proposed prediction model can list all the probable architectures of the priority Address-Encoder and Reset-Decoder readout circuit. In addition, the model is able to highlight the structure that contains the minimum number of transistors, even when the bit-width of the input states of the basic blocks in every layer are different, instead of calculating the number of transistors based on the assumption that the bit-width of the input states of the basic block in every layer are same, like the traditional prediction model. A comparison of the results obtained with the Cadence post-layout simulation and FPGA implementation shows that the number of transistors calculated by the proposed model is of the same order of magnitude to that obtained from the Cadence post-layout simulation and FPGA implementation.