Published December 1, 2008 | Version v1
Journal article

Peak current failure levels in ESD sensitive semiconductor devices and their application in evaluation of materials used in ESD protection. Part 2: Experimental verification

  • 1. VTT Technical Research Centre of Finland, PO Box 1300, FI-33101 Tampere (Finland)
  • 2. Electrostatic Solutions Ltd., 13 Redhill Crescent, Southampton, SO16 7BQ (United Kingdom)

Description

This paper gives experimental demonstration that the method described in Part 1 of the paper, using data from Human Body Model test on devices, can be used to estimate an ESD pulse current threshold for damage to ESD energy susceptible semiconductor devices. The technique is intended for laboratory evaluation of ESD threats from equipment, materials and other ESD sources in the electronics assembly factory environment. The predicted ESD current damage threshold is demonstrated to give a useful boundary to a 'safe' area of ESD current and duration.

Availability note (English)

Available from http://dx.doi.org/10.1088/1742-6596/142/1/012006

Additional details

Publishing Information

Journal Title
Journal of Physics. Conference Series (Online)
Journal Volume
142
Journal Issue
1
Journal Page Range
[6 p.]
ISSN
1742-6596

Conference

Title
12. international conference on electrostatics
Acronym
Electrostatics 2007
Dates
25-29 Mar 2007
Place
Oxford (United Kingdom)

INIS

Country of Publication
United Kingdom
Country of Input or Organization
International Atomic Energy Agency (IAEA)
INIS RN
41053873
Subject category
S42: ENGINEERING;
Resource subtype / Literary indicator
Conference
Descriptors DEI
DAMAGE; ELECTRIC CURRENTS; ELECTROSTATICS; EVALUATION; FAILURES; OCCUPATIONAL SAFETY; PULSES; SAFETY ENGINEERING; SEMICONDUCTOR DEVICES
Descriptors DEC
CURRENTS; ENGINEERING; SAFETY