Design and characterisation of an LGAD detector read-out chip for picosecond time-of-flight measurement for ATLAS experiment

The development of a new detector, namely Low Gain Avalanche Diode (LGAD) opens the way to obtaining picosecond level timing information for pixel sensors. Both ATLAS and CMS at CERN rely on such detectors to extract precise timing information from the collisions. While operated in phase 3, these detectors will reduce the pileup confusion in the high luminosity regime. Such a new detectors require a new generation of readout ASICs in order to bring the time resolution to the required levels which is several orders of magnitude better than what is currently achieved. Developed within the ATLAS collaboration, ALTIROC ASIC is based on GHz amplifiers and Time-to-Digital Converters (TDC) with performance and power budget beyond current state-of-the-art. The different jitter components restraining the time resolution are exposed and evaluated. Also, the ASIC must sustain unprecedented radiation levels (several hundred of Mrads). This thesis deals with Single Event Effects affecting the Phase-Locked Loop (PLL), a highly sensitive element on the clock path. Finally, ALTIROC's simulation and characterisation (when coupled to an LGAD) are compared with another ASIC coupled to a silicon photo-multiplier (SiPM). (author)