A 5 Gb/s low area CDR for embedded clock serial links

A multi-standard compatible clock and data recovery circuit (CDR) with a programmable equalizer and wide tracking range is presented. Considering the jitter performance, tracking range and chip area, the CDR employs a first-order digital loop filter, two 6-bit DACs and high linearity phase interpolators to achieve high phase resolution and low area. Meanwhile the tracking range is greater than ±2200 ppm, making this proposed CDR suitable for the embedded clock serial links. A test chip was fabricated in the 55 nm CMOS process. The measurements show that the test chip can achieve BER < 10⁻¹² and meet the jitter tolerance specification. The test chip occupies 0.19 mm² with a 0.0486 mm² CDR core, which only consumes 30 mW from a 1.2 V supply at 5 Gb/s. (semiconductor integrated circuits)