A Preliminary Verification and Validation (V and V) Methodology for the Artifacts Programmed with a Hardware Description Language (HDL)

Nowadays, the FPGA (Field Programmable Gate Array) is widely used in various fields of industry. The FPGA was evolved from the technology of PLD (Programmable Logic Device). The FPGA provides more logic gates than the PLD, which integrates millions of programmable logic gates into a chip. It also provides a massive, fast and reliable processing performance. So, we can integrate a system's functions into a FPGA, which can be a SoC (System on Chip). Furthermore, we can make a FPGA-based DSP, which DSP functions are implemented with a FPGA. With these merits, the FPGA is also used in the nuclear industry. For example, the safety-critical I and C component is manufactured with the FPGA. The FPGA is programmed with a HDL. The quality of the artifacts programmed with a HDL can impact on the quality of a FPGA. When a hazard fault exists in the artifact of a FPGA and is activated during its operation, an accident caused by the fault in the FPGA occurs. So, it is necessary to ensure the quality of the artifacts. This paper, for the purpose of applying it to the SMART (System-integrated Modular Advanced ReacTor) MMIS project, is to present a preliminary V and V methodology for HDL programmed artifacts. For this, we reviewed the following items: - Characteristics of HDL programming - Applicable requirements for a HDL program used for the safety-critical systems - Fault modes of a FPGA Based on the review, we establish the preliminary V and V methodology