Readout electronics for CSR-ETF silicon strip array detector system

A readout electronics has been developed for the silicon strip array detector system of HIRFL-CSR-ETF. It consists of 48 front end electronics (FEE) boards, 12 PXI-DAQ boards and one trigger board. It can implement energy and time measurements of 4608 channels. Each FEE board is based on 6 ASICs (ATHED), which implements energy and time measurements of 96 channels. The PXI-DAQ board meets requirements of high-speed counting and amount of readout channels and can process signals of 4 FEEs. The trigger board is developed to select the valid events. The energy linearity of the readout electronics is better than 0.3% in the dynamic range of 0.1-0.7 V. In the test with a standard triple alpha source, the energy resolution was 1.8% at 5.48 MeV. This readout electronics enables the silicon strip array system to identify particles of A ≤ 14. (authors)