Published December 2022
| Version v1
Book
Design and characterization of leakage current compensation circuit for semiconductor detectors
Creators
- 1. Variable Energy Cyclotron Centre, 1/AF Bidhan Nagar, Kolkata – 700064 (India)
Description
The noise optimization of CMOS-based front-end electronics for semiconductor based detector readout consists of current and voltage noise minimization in the design of Charge Sensitive pre-Amplifier (CSA). The tested LCC design has been integrated in the second version of GMDA ASIC. Layout design, verification are completed. The final tape-out is being sent to the foundry for fabrication
Additional details
Publishing Information
- Publisher
- Cotton University
- Imprint Place
- Guwahati (India)
- Imprint Title
- Proceedings of the DAE-BRNS symposium on nuclear physics. V. 66
- Imprint Pagination
- [1318 p.]
- Journal Page Range
- [2 p.]
Conference
- Title
- 66. DAE-BRNS symposium on nuclear physics
- Dates
- 1-5 Dec 2022
- Place
- Guwahati (India)
INIS
- Country of Publication
- India
- Country of Input or Organization
- India
- INIS RN
- 54038058
- Subject category
- S46: INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY;
- Resource subtype / Literary indicator
- Conference
- Descriptors DEI
- CMOS CIRCUITS; DESIGN; FEASIBILITY STUDIES; LEAKAGE CURRENT; MOSFET; READOUT SYSTEMS; SPECIFICATIONS
- Descriptors DEC
- CURRENTS; ELECTRIC CURRENTS; ELECTRONIC CIRCUITS; FIELD EFFECT TRANSISTORS; INTEGRATED CIRCUITS; MICROELECTRONIC CIRCUITS; MOS TRANSISTORS; SEMICONDUCTOR DEVICES; TRANSISTORS
Optional Information
- Notes
- Article No. G32