Processes in N-channel MOSFETs during postirradiation thermal annealing

The processes during postirradiation thermal annealing of γ-ray irradiated n-channel MOSFETs with both wet and dry gate oxides are investigated. For both analysed technologies, a so-called ''latent'' interface trap buildup is observed, followed at very late annealing times by the decrease in the interface-trap density. A model is proposed that successfully accounts for the experimental results. Implications of observed effects for total dose hardness assurance test methods implementation are discussed. (author)