Design and Implementation of Hybrid Multiple Valued Logic Error Detector using Single Electron Transistor and CMOS at 120 nm Technology

Hybridization of single electron transistor with MOSFET using quaternary logic for the design of Down Literal circuits are introduced here due to which the number of components as well as interconnection complexity will gets reduced just by designing the proper values of components of individual SET such as capacitor and resistors and by changing the values of W/L ratio of MOSFETS. This DLC's are used for the design of hybrid quaternary logic error detector and verified by CADENCE Tool. (paper)