Published March 2010
| Version v1
Journal article
Verification of soft-error rate estimation method in a logic LSI
Creators
- 1. Japan Atomic Energy Agency, Quantum Beam Science Directorate, Takasaki, Gunma (Japan)
- 2. Japan Aerospace Exploration Agency, Sagamihara, Kanagawa (Japan)
Description
SET-induced soft-error rates (SERSET) in logic LSIs are estimated from SET pulse-widths measured in logic cells used in logic LSIs. The estimated rates are consistent with directly measured SERSETs for logic LSIs. (author)
Additional details
Publishing Information
- Journal Title
- Hosei Daigaku Ion Bimu Kogaku Kenkyusho Hokoku
- Journal Issue
- suppl.28
- Journal Page Range
- p. 35-40
- ISSN
- 0286-0201
Conference
- Title
- 28. symposium on materials science and engineering
- Dates
- 9 Dec 2009
- Place
- Koganei, Tokyo (Japan)
INIS
- Country of Publication
- Japan
- Country of Input or Organization
- Japan
- INIS RN
- 42006923
- Subject category
- S46: INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY;
- Resource subtype / Literary indicator
- Conference
- Descriptors DEI
- CROSS SECTIONS; ERRORS; FAULT TOLERANT COMPUTERS; FLIP-FLOP CIRCUITS; INTEGRATED CIRCUITS; LOGIC CIRCUITS; PHYSICAL RADIATION EFFECTS; PULSE TECHNIQUES; RELIABILITY; SEMICONDUCTOR DEVICES; TESTING; TRANSIENTS
- Descriptors DEC
- COMPUTERS; DIGITAL COMPUTERS; ELECTRONIC CIRCUITS; MICROELECTRONIC CIRCUITS; MULTIVIBRATORS; PULSE CIRCUITS; RADIATION EFFECTS
Optional Information
- Notes
- 9 refs., 4 figs.