Intelligent three-dimensional chip-stacking process for pixel detectors for high energy physics experiments

An intelligent and unique three-dimensional (3D) chip stacking process is proposed for pixel detectors for high energy physics experiments. In this process, a chip-on-chip bonding scheme with base chips fabricated in silicon-on-insulator (SOI) technology is considered instead of a wafer-on-wafer scheme to address the process feasibility for shuttle-run chips. Au micro cylinder-shaped bumps with a 3 µm diameter were newly developed. Low via resistance of approximately 0.37 Ω/via was achieved. Instead of generally used through-silicon-vias, submicron through-buried-oxide vias were fabricated in the SOI wafer process similar to that for the pixel sense nodes. The nodes are used as vias connecting the upper and lower chip circuits after etching off the handle wafer silicon of the upper chip. A pixel detector fabricated using this 3D process successfully detected β-ray tracks from ⁹⁰Sr, showing a via yield of more than 99%. (author)