FPGA based implementation of the communication interface between CPU and Multi-MII

Communication interface between embedded CPU and two channel data acquisition systems was implemented based on FPGA. These two channel data acquisition systems were 220 meters away and the peak data rate was 24Mbps per channel. FPGA was used to expand embedded CPU's MII (Media Independent Interface) into two MII which worked at a nonstandard bit rate (40Mbps), communicated with two long range Ethernet transceiver and received data from these two channel data acquisition systems. The data was merged by FPGA and transmitted to embedded CPU through CPU's MII. The whole logic design was implemented in Xilinx's XC3S100E device, verified on the hardware test platform based on an ARM chip (S3C4510B) and worked well in practice. (authors)