The data handling processor of the Belle II DEPFET detector

A two layer highly granular DEPFET pixel detector will be operated as the innermost subsystem of the Belle II experiment, at the new Japanese super flavor factory (SuperKEKB). Such a finely segmented system will allow to improve the vertex reconstruction in such ultra high luminosity environment but, at the same time, the raw data stream generated by the 8 million pixel detector will exceed the capability of real-time processing due to its high rate. For this reason a new ASIC, the Data Handling Processor (DHP) is designed to provide full functionality of data processing at the level of the front-end electronics and to cover the task of controling the pixel read-out scheme. In this contribution, the description of the latest prototype chip in TSMC 65 nm technology together with the latest test results of the interface functionality are presented.