A method for characterizing a microprocessor's vulnerability to SEU

The authors have developed a system that tests microprocessors for single event upset (SEU) at the specified clock speed and without adding wait or hold states. This system compiles a detailed record of SEU induced errors and has been used to test the Sandia SA3000 microprocessor and prototypes of its commercial equivalent, the Harris H80C85 at the Lawrence Berkeley Laboratory 88-inch cyclotron facility. Using appropriate test programs and analyzing the resulting upset data, the authors have established the SEU cross-section of the major functional elements of the hardened processors. With these cross-sections and the estimated duty factors of a typical program, the authors computed the expected upset rate in a parallel, normally incident beam as a function of linear energy transfer (LET), and measured the rate in several cyclotron beams. Good agreement between the measured and calculated rates was obtained