The phase-locked loop algorithm of the function generation/controller

This paper describes the phase-locked loop algorithms that are used by the real-time power converter controllers at CERN. The algorithms allow the recovery of the machine time and events received by an embedded controller through WorldFIP or Ethernet-based fieldbuses. During normal operation, the algorithm provides less than 10 µs of time precision and 0.5 µs of clock jitter for the WorldFIP case, and less than 2.5 µs of time precision and 40 ns of clock jitter for the Ethernet case. (author)