Optimizing the radiation hardness of a Si-gate CMOS process

Certain defense and nuclear-reactor system scenarios require VLSI ICs that are hardened to ionizing radiation levels above 10 Mrad. Although low-power metal-gate CMOS ICs can be hardened to 10 Mrad, the high packing densities and performance required by VLSI ICs are achievable only by using a Si-gate technology. To date, Si-gate ICs have been hardened to the 1-Mrad level by means of special processing. This paper presents a new way of optimizing the hardness of parts produced by a Si-gaet CMOS process. This new approach has resulted in the development of a VLSI process that consistently yields 10-Mrad hardened Si-gate ICs