Radiation Hardening Techniques for a Preamplifier with Layout Strategy and Size Optimization

For many decades, various radiation-hardened-by-design (RHBD) techniques have been developed to meet the design requirements of irradiating environment in nuclear power plants. Improvements on the circuit side for radiation sensors in performance, chip size, and radiation hardening ability have been adopted in current plant systems; however, next generation reactors and/or preparation for severe events in existing reactors require advanced circuit structures that can provide relatively long viability in harsh conditions. Preamplifier are essential components used to bridge two different signal-processing worlds between physical data from sensors and digital expression for human recognition. When radiation is injected into Metal Oxide Semiconductor Field Effect Transistor (MOSFET), Electron-Hole Pairs (EHP) are formed in the oxide layer and behaves like an insulator in the semiconductor, where it lead to changes in the device parameters due to trapped holes with low mobility inside the oxide layer. This results in TID which destroys the device, as Single Event Effect (SEE) also causes malfunction by triggering threshold voltage shift and leakage current. In this paper, modification of standard MOSFET layouts, Bipolar Complementary Metal-oxide Semiconductor (BiCMOS) circuit and variable channel length & width of MOSFETs suggest radiation hardening methods. These scheme have many strong advantages at using commercial MOSFET fabrications through simple active layer modifications without special fabrications such as Gate-Enclosed layouts MOSFETs, large gate MOSFETs. In this paper, the proposed MOSFET layout and size optimizations for, robustness to radiation, are presented. Furthermore, the proposed MOSFET layouts provide advantages in simple modification from the standard fabrications, simply adaptable for radiation hardening integrated circuit applications in terms of threshold voltage shift and leakage current.