Test runs of a Belle II PXD prototype readout system

The Belle II PXD readout system (called ONSEN for Online Selection Nodes) uses ATCA (Advanced Telecommunications Architecture) boards with Xilinx Virtex-5 FX70T FPGAs and high speed optical links (6.5 Gbit/s each). The full system consists of 9 carrier boards and 33 daughter cards. The ONSEN system has several interfaces: (a) it receives PXD data from the DHH (Data Handling Hybrid) system, (b) it receives ROI (Regions-of-Interest) data for online data reduction from the HLT (High Level Trigger) system by GbE, and (c) it features data ports to two event builders: EVB1 combines data from all detectors except PXD (in order to generate the ROIs) and EVB2 combines the reduced PXD data with all other data. One of the critical issues is the matching of trigger numbers in the data (received by DHH from the timing distribution system) and trigger numbers in the ROIs (received by the HLT). In order to test the interfaces, in particular for a high HLT rate up to 30 kHz, a prototype system with 3 daughter cards was installed at KEK and tested with DHH, HLT and EVB2. Test results are presented.