Performance Analysis of a novel Fusion Adder/Subtractor design

This paper proposes a novel fusion 1bit Adder/Subtractor design using the CMOS transistor. The proposed novel fusion 1 bit Adder/Subtractor is utilized in the design of parallel adder/subtractor with the resolution upto 27 bits. Though there are several design technologies like static CMOS logic, Dynamic CMOS, CPL, Transmission Gate Array, the proposed Fusion Design is advantageous for minimized chip area, low power consumption and high speed of operation. In this work, two circuit topologies are proposed by utilizing the 8T and 12T XOR CMOS design for the novel Fusion Adder/Subtractor. This paper compares the parametric values of power, delay and area with the existing methods. The proposed design is developed using the Cadence Virtuoso Tool with the technology of 45 nm. The proposed fusion design exhibits low power and delay as the resolution of the design is increased. Also the chip area is 0.3138µm2 for the 28T FAS circuit and 0.165 µm2 for the proposed 24T FAS circuit. (paper)