Post-gate plasma and sputter process effects on the radiation hardness of metal gate CMOS integrated circuits

With the decreasing dimensions of todays IC's, more attention is being directed towards plasma processing for process simplification and improved control of dimensional tolerances. The desire for high reliability automated assembly techniques has led to the development of the gold bump technology for tape automated bonding. Furthermore, the development of the beam-lead technology continues. All these developments lead to increased use of plasma and sputter processes; therefore, the impact of these processes on radiation hardness must be evaluated. The devices employed in this investigation are CMOS 4007 inverters. They were processed according to the optimized baseline process sequence through Al sinter except that no gate oxide anneal was used. The gate oxide thickness was 700 A. Substrate and p-well resistivities were chosen to give preirradiation p-channel and n-channel thresholds of -2.0 and +3.0 volts respectively. The γ-induced threshold voltage shifts are plotted as a function of the irradiation dose