A simple and robust niobium Josephson junction integrated circuit process

This paper reports on a simple and robust process for fabricating low-Tc Josephson junction integrated circuits that has been developed. The process is designed around the NB/Al2O3--Al/Nb trilayer, and utilizes nine masking steps to form two separate levels of trilayer Josephson junctions, as well as resistors, capacitors, and transmission lines. Materials used for interresistors, capacitors, and transmission lines. Materials used for interlayer dielectrics and passivation layers are silicon dioxide and silicon nitride formed by Plasma Enhanced Chemical vapor Deposition (PECVD). The PECVD equipment that we use yields a high deposition rate at moderate substrate temperatures. The authors see no degradation of the junction characteristic due to these depositions. The measured loss tangent of this dielectric at 10 GHz using a parallel plate technique in 4.44 x 10-4