Published September 28, 2014 | Version v1
Journal article

Extremely scaled high-k/In0.53Ga0.47As gate stacks with low leakage and low interface trap densities

  • 1. Materials Department, University of California, Santa Barbara, California 93106-5050 (United States)

Description

Highly scaled gate dielectric stacks with low leakage and low interface trap densities are required for complementary metal-oxide-semiconductor technology with III-V semiconductor channels. Here, we show that a novel pre-deposition technique, consisting of alternating cycles of nitrogen plasma and tetrakis(dimethylamino)titanium, allows for HfO2 and ZrO2 gate stacks with extremely high accumulation capacitance densities of more than 5 μF/cm2 at 1 MHz, low leakage current, low frequency dispersion, and low midgap interface trap densities (1012 cm−2 eV−1 range). Using x-ray photoelectron spectroscopy, we show that the interface contains TiO2 and small quantities of In2O3, but no detectable Ga- or As-oxides, or As-As bonding. The results allow for insights into the microscopic mechanisms that control leakage and frequency dispersion in high-k/III-V gate stacks.

Additional details

Identifiers

Publishing Information

Journal Title
Journal of Applied Physics
Journal Volume
116
Journal Issue
12
Journal Page Range
p. 124104-124104.8
ISSN
0021-8979
CODEN
JAPIAU

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