High-step-coverage Cu-lateral interconnections over 100 µm thick chips on a polymer substrate—an alternative method to wire bonding

We propose a novel chip in the polymer board interconnect method for packaging different kinds of chips on a wafer level, where conventional wire bonding may not be possible due to either space or mechanical constraints. High-step-coverage copper (Cu)-lateral interconnects formed over 100 µm thick Si chips by the electroplating method have been investigated for their microstructure and electrical characteristics, using the field emission scanning electron microscope and semiconductor parameter analyzer (Agilent, 4156C). The obtained coverage ratios (i.e. the layer thickness on the chip surface to the sidewall of the chip) for each formed layer, i.e. the tantalum barrier layer, Cu seed layer, SiO₂ dielectric layer and electroplated Cu layer, were 3:1, 3:1, 1.5:1 and 1:1, respectively. The measured mean electrical resistances for 36 µm × 2000 µm and 58 µm × 2000 µm interconnect lines were respectively 31.1 and 24 mΩ, and the difference between measured and calculated resistance values was less than 5%. The good quality of as-fabricated Cu-lateral interconnects was evidenced from the observed low resistance values for isolated interconnects and the linear change in daisy chain resistance with the number of interconnects. More importantly, even at a high operating temperature of 150 °C, the resistance value of the Cu-lateral interconnect over the integrated chip was very close to that of the resistance value of interconnect on the plain wafer. The suitability of this technique in integrating various chips heterogeneously was validated from the no observed change in transistor behavior due to this technique. Since this is a CMOS compatible interconnection method between the polymer substrate and chip, it can readily be scaled up to the wafer level. (paper)